This blog describes the details of the middle PCI Express architectural layer, the Data Link Layer. The Data Link Layer's main responsible is "error detection and correction as well as link management support".
The Data Link Layer serves as the "gatekeeper" for each individual link within a PCI Express system. It ensures that the data being sent back and forth across the link is correct and received in the same order it was sent. The Data Link Layer makes sure that each packet makes it across the link, and makes it across intact. This layer takes TLPs from the transmit side of the Transaction Layer and continues the process of building them into a PCI Express transaction.
The Data Link Layer adds a sequence number to the front of the packet and an LCRC error checker to the tail. Once the transmit side of
For incoming TLPs, the Data Link Layer accepts the from the Physical Layer and checks the sequence number and LCRC make sure the TLP is correct. If it is correct, the Data Link Layer the sequence number and LCRC, then passes the TLP up to the side of the Transaction Layer. If an error is detected (either wrong sequence number or LCRC does not match), the Data Link Layer does not pass the "bad" packet on to the Transaction Layer. Instead, the Data Layer communicates with its link mate to try and resolve the through a retry attempt.
The Data Link Layer only passes a TLP through to the Transaction Layer if the packet's sequence number and LCRC values check out. It is important to note this because this "gate-keeping' lows the Transaction Layer to assume that everything it receives from link is correct. Below figure gives the clear idea, the Data Link Layer forwards outgoing transactions from the Transaction Layer to the Physical Layer, and coming transactions from the Physical Layer to the Transaction Layer.
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